HCS12 datasheet(211/452 Pages) FREESCALE

211 / 452 page

Glossary

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

211

Operation:

(PC) + $0004

⇒ PC

Description:

Never branches. LBRN is effectively a 4-byte NOP that requires three

cycles to execute. LBRN is included in the instruction set to provide a

complement to the LBRA instruction. The instruction is useful during

program debug, to negate the effect of another branch instruction without

disturbing the offset byte. A complement for LBRA is also useful in compiler

implementations.

Execution time is longer when a conditional branch is taken than when it is

not, because the instruction queue must be refilled before execution

resumes at the new address. Since the LBRN branch condition is never

satisfied, the branch is never taken, and the queue does not need to be

refilled, so execution time is always the smaller value.

LBRN

Long Branch Never

LBRN

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

LBRN rel16

REL

18 21 qq rr

OPO

HCS12 数据表(PDF) 211 Page - Freescale Semiconductor, Inc

HCS12 数据表(HTML) 211 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载