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HCS12 数据表(PDF) 43 Page - Freescale Semiconductor, Inc

部件名 HCS12
功能描述  HCS12 Microcontrollers
PDF  452 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

HCS12 数据表(HTML) 43 Page - Freescale Semiconductor, Inc

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S12CPUV2 Reference Manual, Rev. 4.0
Freescale Semiconductor
43
Example:
1000
18 09 C2 20 00
MOVB
$2000 2,PC
Moves a byte of data from $2000 to $1009
The expected location of the PC = $1005. The offset = +2.
[1005 + 2 (for 2,PC) + 2 (for correction) = 1009]
$18 is the page pre-byte, 09 is the MOVB opcode for ext-idx, C2 is the
indexed postbyte for 2,PC (without correction).
The Freescale MCUasm assembler produces corrected object code for
PC-relative moves (18 09 C0 20 00 for the example shown).
NOTE:
Instead of assembling the 2,PC as C2, the correction has been applied to
make it C0. Check whether an assembler makes the correction before using
PC-relative moves.
On the newer HCS12, the instruction queue was implemented such that an
internal pointer, to the start of the next instruction, is always available. On
the HCS12, PC-relative move instructions work as expected without any
offset adjustment. Although this is different from the original M68HC12, it is
unlikely to be a problem because PC-relative indexing is rarely, if ever, used
with move instructions.
3.10.2 Bit Manipulation Instructions
Bit manipulation instructions use either a combination of two or a
combination of three addressing modes.
The clear bits in memory (BCLR) and set bits in memory (BSET) instructions
use an 8-bit mask to determine which bits in a memory byte are to be
changed. The mask must be supplied with the instruction as an immediate
mode value. The memory location to be modified can be specified by means
of direct, extended, or indexed addressing modes.
The branch if bits cleared (BRCLR) and branch if bits set (BRSET)
instructions use an 8-bit mask to test the states of bits in a memory byte. The
mask is supplied with the instruction as an immediate mode value. The
memory location to be tested is specified by means of direct, extended, or
indexed addressing modes. Relative addressing mode is used to determine
the branch address. A signed 8-bit offset must be supplied with the
instruction.



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