HCS12 datasheet(41/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

3.9.7 Accumulator D Indirect Indexed Addressing

This indexed addressing mode adds the value in the D accumulator to the

value in the base index register to form the address of a memory location

that contains a pointer to the memory location affected by the instruction.

The instruction operand does not point to the address of the memory

location to be acted upon, but rather to the location of a pointer to the

address to be acted upon. The square brackets distinguish this addressing

mode from D accumulator offset indexing.

Examples:

JMP

[D,PC]

GO1

DC.W

PLACE1

GO2

DC.W

PLACE2

GO3

DC.W

PLACE3

This example is a computed GOTO. The values beginning at GO1 are

addresses of potential destinations of the jump (JMP) instruction. At the time

the JMP [D,PC] instruction is executed, PC points to the address GO1, and

D holds one of the values $0000, $0002, or $0004 (determined by the

program some time before the JMP).

Assume that the value in D is $0002. The JMP instruction adds the values

in D and PC to form the address of GO2. Next the CPU reads the address

PLACE2 from memory at GO2 and jumps to PLACE2. The locations of

PLACE1 through PLACE3 were known at the time of program assembly but

the destination of the JMP depends upon the value in D computed during

program execution.

3.10 Instructions Using Multiple Modes

Several CPU12 instructions use more than one addressing mode in the

course of execution.

3.10.1 Move Instructions

Move instructions use separate addressing modes to access the source and

destination of a move. There are move variations for all practical

combinations of immediate, extended, and indexed addressing modes.

The only combinations of addressing modes that are not allowed are those

with an immediate mode destination (the operand of an immediate mode

instruction is data, not an address). For indexed moves, the reference index

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