HCS12 datasheet(47/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

4.1 Introduction

The CPU12 uses an instruction queue to increase execution speed.

This section describes queue operation during normal program execution

and changes in execution flow. These concepts augment the descriptions of

instructions and cycle-by-cycle instruction execution in subsequent

sections, but it is important to note that queue operation is automatic, and

generally transparent to the user.

The material in this section is general. Section 6. Instruction Glossary

contains detailed information concerning cycle-by-cycle execution of each

instruction. Section 8. Instruction Queue contains detailed information

about tracking queue operation and instruction execution.

4.2 Queue Description

The fetching mechanism in the CPU12 is best described as a queue rather

than as a pipeline. Queue logic fetches program information and positions it

for execution, but instructions are executed sequentially. A typical pipelined

central processor unit (CPU) can execute more than one instruction at the

same time, but interactions between the prefetch and execution

mechanisms can make tracking and debugging difficult. The CPU12 thus

gains the advantages of independent fetches, yet maintains a

straightforward relationship between bus and execution cycles.

Each instruction refills the queue by fetching the same number of bytes that

the instruction uses. Program information is fetched in aligned 16-bit words.

Each program fetch (P) indicates that two bytes need to be replaced in the

instruction queue. Each optional fetch (O) indicates that only one byte needs

to be replaced. For example, an instruction composed of five bytes does two

program fetches and one optional fetch. If the first byte of the five-byte

instruction was even-aligned, the optional fetch is converted into a free

Reference Manual — S12CPUV2

Section 4. Instruction Queue

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