HCS12 datasheet(79/452 Pages) FREESCALE

79 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

5.22 Interrupt Instructions

Interrupt instructions handle transfer of control to a routine that performs a

critical task. Software interrupts are a type of exception. Section 7.

Exception Processing covers interrupt exception processing in detail.

The software interrupt (SWI) instruction initiates synchronous exception

processing. First, the return PC value is stacked. After CPU context is

stacked, execution continues at the address pointed to by the SWI vector.

Execution of the SWI instruction causes an interrupt without an interrupt

service request. SWI is not inhibited by global mask bits I and X in the CCR,

and execution of SWI sets the I mask bit. Once an SWI interrupt begins,

maskable interrupts are inhibited until the I bit in the CCR is cleared. This

typically occurs when a return from interrupt (RTI) instruction at the end of

the SWI service routine restores context.

The CPU12 uses a variation of the software interrupt for unimplemented

opcode trapping. There are opcodes in all 256 positions in the page 1

opcode map, but only 54 of the 256 positions on page 2 of the opcode map

Table 5-21. Jump and Subroutine Instructions

Mnemonic

Function

Operation

BSR

Branch to subroutine

SP – 2

⇒ SP

RTNH : RTNL ⇒ M(SP) : M(SP+1)

Subroutine address

⇒ PC

CALL

Call subroutine

in expanded memory

SP – 2

⇒ SP

RTNH:RTNL⇒ M(SP) : M(SP+1)

SP – 1

⇒ SP

(PPAGE)

⇒ M(SP)

Page

⇒ PPAGE

Subroutine address

⇒ PC

JMP

Jump

Address

⇒ PC

JSR

Jump to subroutine

SP – 2

⇒ SP

RTNH : RTNL⇒ M(SP) : M(SP+1)

Subroutine address

⇒ PC

RTC

Return from call

M(SP) ⇒ PPAGE

+ 1 ⇒ SP

M(SP) : M(SP+1) ⇒ PCH : PCL

+ 2 ⇒ SP

RTS

Return from subroutine

M(SP) : M(SP+1) ⇒ PCH : PCL

+ 2 ⇒ SP

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