HCS12 datasheet(25/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

2.2.5.2 X Mask Bit

The XIRQ input is an updated version of the NMI input found on earlier

generations of MCUs. Non-maskable interrupts are typically used to deal

with major system failures, such as loss of power. However, enabling

non-maskable interrupts before a system is fully powered and initialized can

lead to spurious interrupts. The X bit provides a mechanism for enabling

non-maskable interrupts after a system is stable.

By default, the X bit is set to 1 during reset. As long as the X bit remains set,

interrupt service requests made via the XIRQ pin are not recognized. An

instruction must clear the X bit to enable non-maskable interrupt service

requests made via the XIRQ pin. Once the X bit has been cleared to 0,

software cannot reset it to 1 by writing to the CCR. The X bit is not affected

by maskable interrupts.

When an XIRQ interrupt occurs after non-maskable interrupts are enabled,

both the X bit and the I bit are set automatically to prevent other interrupts

from being recognized during the interrupt service routine. The mask bits

are set after the registers are stacked, but before the interrupt vector is

fetched.

Normally, a return-from-interrupt (RTI) instruction at the end of the interrupt

service routine restores register values that were present before the

interrupt occurred. Since the CCR is stacked before the X bit is set, the RTI

normally clears the X bit, and thus re-enables non-maskable interrupts.

While it is possible to manipulate the stacked value of X so that X is set after

an RTI, there is no software method to reset X (and disable XIRQ) once X

has been cleared.

2.2.5.3 H Status Bit

The H bit indicates a carry from accumulator A bit 3 during an addition

operation. The DAA instruction uses the value of the H bit to adjust a result

in accumulator A to correct BCD format. H is updated only by the add

accumulator A to accumulator B (ABA), add without carry (ADD), and add

with carry (ADC) instructions.

2.2.5.4 I Mask Bit

The I bit enables and disables maskable interrupt sources. By default, the I

bit is set to 1 during reset. An instruction must clear the I bit to enable

maskable interrupts. While the I bit is set, maskable interrupts can become

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