HCS12 datasheet(34/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

8-bit, 9-bit, and 16-bit offsets are signed two’s complement numbers to

support branching upward and downward in memory. The numeric range of

short branch offset values is $80 (–128) to $7F (127). Loop primitive

instructions support a 9-bit offset which allows a range of $100 (–256) to

$0FF (255). The numeric range of long branch offset values is $8000

(–32,768) to $7FFF (32,767). If the offset is 0, the CPU executes the

instruction immediately following the branch instruction, regardless of the

test involved.

Since the offset is at the end of a branch instruction, using a negative offset

value can cause the program counter (PC) to point to the opcode and initiate

a loop. For instance, a branch always (BRA) instruction consists of two

bytes, so using an offset of $FE sets up an infinite loop; the same is true of

a long branch always (LBRA) instruction with an offset of $FFFC.

An offset that points to the opcode can cause a bit-condition branch to

repeat execution until the specified bit condition is satisfied. Since

bit-condition branches can consist of four, five, or six bytes depending on

the addressing mode used to access the byte in memory, the offset value

that sets up a loop can vary. For instance, using an offset of $FC with a

BRCLR that accesses memory using an 8-bit indexed postbyte sets up a

loop that executes until all the bits in the specified memory byte that

correspond to 1s in the mask byte are cleared.

3.9 Indexed Addressing Modes

The CPU12 uses redefined versions of M68HC11 indexed modes that

reduce execution time and eliminate code size penalties for using the Y

index register. In most cases, CPU12 code size for indexed operations is the

same or is smaller than that for the M68HC11. Execution time is shorter in

all cases. Execution time improvements are due to both a reduced number

of cycles for all indexed instructions and to faster system clock speed.

The indexed addressing scheme uses a postbyte plus zero, one, or two

extension bytes after the instruction opcode. The postbyte and extensions

do the following tasks:

1. Specify which index register is used

2. Determine whether a value in an accumulator is used as an offset

3. Enable automatic pre- or post-increment or pre- or post-decrement

4. Specify size of increment or decrement

5. Specify use of 5-, 9-, or 16-bit signed offsets

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