HCS12 datasheet(55/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

5.1 Introduction

This section contains general information about the central processor unit

(CPU12) instruction set. It is organized into instruction categories grouped

by function.

5.2 Instruction Set Description

CPU12 instructions are a superset of the M68HC11 instruction set. Code

written for an M68HC11 can be reassembled and run on a CPU12 with no

changes. The CPU12 provides expanded functionality and increased code

efficiency. There are two implementations of the CPU12, the original

M68HC12 and the newer HCS12. Both implementations have the same

instruction set, although there are small differences in cycle-by-cycle access

details (the order of some bus cycles changed to accommodate differences

in the way the instruction queue was implemented). These minor

differences are transparent for most users.

In the M68HC12 and HCS12 architecture, all memory and input/output (I/O)

are mapped in a common 64-Kbyte address space (memory-mapped I/O).

This allows the same set of instructions to be used to access memory, I/O,

and control registers. General-purpose load, store, transfer, exchange, and

move instructions facilitate movement of data to and from memory and

peripherals.

The CPU12 has a full set of 8-bit and 16-bit mathematical instructions.

There are instructions for signed and unsigned arithmetic, division, and

multiplication with 8-bit, 16-bit, and some larger operands.

Special arithmetic and logic instructions aid stacking operations, indexing,

binary-coded decimal (BCD) calculation, and condition code register

manipulation. There are also dedicated instructions for multiply and

Reference Manual — S12CPUV2

Section 5. Instruction Set Overview

HCS12 数据表(PDF) 55 Page - Freescale Semiconductor, Inc