HCS12 datasheet(96/452 Pages) FREESCALE

96 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

n — Write 8-bit PPAGE register. These cycles are used

only with the CALL and RTC instructions to write the

destination value of the PPAGE register and are not

visible on the external bus. Since the PPAGE register

is an internal 8-bit register, these cycles are never

stretched.

O — Optional cycle. Program information is always fetched

as aligned 16-bit words. When an instruction consists

of an odd number of bytes, and the first byte is

misaligned, an O cycle is used to make an additional

program word access (P) cycle that maintains queue

order. In all other cases, the O cycle appears as a free

(f) cycle. The $18 prebyte for page two opcodes is

treated as a special 1-byte instruction. If the prebyte is

misaligned, the O cycle is used as a program word

access for the prebyte; if the prebyte is aligned, the O

cycle appears as a free cycle. If the remainder of the

instruction consists of an odd number of bytes,

another O cycle is required some time before the

instruction is completed. If the O cycle for the prebyte

is treated as a P cycle, any subsequent O cycle in the

same instruction is treated as an f cycle; if the O cycle

for the prebyte is treated as an f cycle, any

subsequent O cycle in the same instruction is treated

as a P cycle. Optional cycles used for program word

accesses can be extended to two bus cycles if the

MCU is operating with an 8-bit external data bus and

the program is stored in external memory. There can

be additional stretching when the address space is

assigned to a chip-select circuit programmed for slow

memory. Optional cycles used as free cycles are

never stretched.

P — Program word access. Program information is fetched

as aligned 16-bit words. These cycles are extended to

two bus cycles if the MCU is operating with an 8-bit

external data bus and the program is stored

externally. There can be additional stretching when

the address space is assigned to a chip-select circuit

programmed for slow memory.

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