HCS12 datasheet(33/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

3.7 Extended Addressing Mode

In this addressing mode, the full 16-bit address of the memory location to be

operated on is provided in the instruction. This addressing mode can be

used to access any location in the 64-Kbyte memory map.

Example:

LDAA

$F03B

This is a basic example of extended addressing. The value from address

$F03B is loaded into the A accumulator.

3.8 Relative Addressing Mode

The relative addressing mode is used only by branch instructions. Short and

long conditional branch instructions use relative addressing mode

exclusively, but branching versions of bit manipulation instructions (branch

if bits set (BRSET) and branch if bits cleared (BRCLR)) use multiple

addressing modes, including relative mode. Refer to

3.10 Instructions Using Multiple Modes for more information.

Short branch instructions consist of an 8-bit opcode and a signed 8-bit offset

contained in the byte that follows the opcode. Long branch instructions

consist of an 8-bit prebyte, an 8-bit opcode, and a signed 16-bit offset

contained in the two bytes that follow the opcode.

Each conditional branch instruction tests certain status bits in the condition

code register. If the bits are in a specified state, the offset is added to the

address of the next memory location after the offset to form an effective

address, and execution continues at that address. If the bits are not in the

specified state, execution continues with the instruction immediately

following the branch instruction.

Bit-condition branches test whether bits in a memory byte are in a specific

state. Various addressing modes can be used to access the memory

location. An 8-bit mask operand is used to test the bits. If each bit in memory

that corresponds to a 1 in the mask is either set (BRSET) or clear (BRCLR),

an 8-bit offset is added to the address of the next memory location after the

offset to form an effective address, and execution continues at that address.

If all the bits in memory that correspond to a 1 in the mask are not in the

specified state, execution continues with the instruction immediately

following the branch instruction.

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