HCS12 datasheet(39/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

3.9.5 Auto Pre/Post Decrement/Increment Indexed Addressing

This indexed addressing mode provides four ways to automatically change

the value in a base index register as a part of instruction execution. The

index register can be incremented or decremented by an integer value

either before or after indexing takes place. The base index register may be

X, Y, or SP. (Auto-modify modes would not make sense on PC.)

Pre-decrement and pre-increment versions of the addressing mode adjust

the value of the index register before accessing the memory location

affected by the instruction — the index register retains the changed value

after the instruction executes. Post-decrement and post-increment versions

of the addressing mode use the initial value in the index register to access

the memory location affected by the instruction, then change the value of the

index register.

The CPU12 allows the index register to be incremented or decremented by

any integer value in the ranges –8 through –1 or 1 through 8. The value

need not be related to the size of the operand for the current instruction.

These instructions can be used to incorporate an index adjustment into an

existing instruction rather than using an additional instruction and increasing

execution time. This addressing mode is also used to perform operations on

a series of data structures in memory.

When an LEAS, LEAX, or LEAY instruction is executed using this

addressing mode, and the operation modifies the index register that is being

loaded, the final value in the register is the value that would have been used

to access a memory operand. (Premodification is seen in the result but

postmodification is not.)

Examples:

STAA

1,–SP

;equivalent to PSHA

STX

2,–SP

;equivalent to PSHX

LDX

2,SP+

;equivalent to PULX

LDAA

1,SP+

;equivalent to PULA

For a “last-used” type of stack like the CPU12 stack, these four examples

are equivalent to common push and pull instructions.

For a “next-available” stack like the M68HC11 stack, push A onto stack

(PSHA) is equivalent to store accumulator A (STAA) 1,SP– and pull A from

stack (PULA) is equivalent to load accumulator A (LDAA) 1,+SP. However,

in the M68HC11, 16-bit operations like push register X onto stack (PSHX)

and pull register X from stack (PULX) require multiple instructions to

decrement the SP by one, then store X, then decrement SP by one again.

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