HCS12 datasheet(97/452 Pages) FREESCALE

97 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

r — 8-bit data read. These cycles are stretched only when

controlled by a chip-select circuit programmed for

slow memory.

R — 16-bit data read. These cycles are extended to two

bus cycles if the MCU is operating with an 8-bit

external data bus and the corresponding data is

stored in external memory. There can be additional

stretching when the address space is assigned to a

chip-select circuit programmed for slow memory.

These cycles are also stretched if they correspond to

misaligned accesses to memory that is not designed

for single-cycle misaligned access.

s — Stack 8-bit data. These cycles are stretched only

when controlled by a chip-select circuit programmed

for slow memory.

S — Stack 16-bit data. These cycles are extended to two

bus cycles if the MCU is operating with an 8-bit

external data bus and the SP is pointing to external

memory. There can be additional stretching if the

address space is assigned to a chip-select circuit

programmed for slow memory. These cycles are also

stretched if they correspond to misaligned accesses

to a memory that is not designed for single cycle

misaligned access. The internal RAM is designed to

allow single cycle misaligned word access.

w — 8-bit data write. These cycles are stretched only when

controlled by a chip-select circuit programmed for

slow memory.

W — 16-bit data write. These cycles are extended to two

bus cycles if the MCU is operating with an 8-bit

external data bus and the corresponding data is

stored in external memory. There can be additional

stretching when the address space is assigned to a

chip-select circuit programmed for slow memory.

These cycles are also stretched if they correspond to

misaligned access to a memory that is not designed

for single-cycle misaligned access.

u — Unstack 8-bit data. These cycles are stretched only

when controlled by a chip-select circuit programmed

for slow memory.

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