HCS12 datasheet(48/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

cycle. If the first byte was odd-aligned, the optional fetch is executed as a

program fetch.

Two external pins, IPIPE[1:0], provide time-multiplexed information about

data movement in the queue and instruction execution. Decoding and use

of these signals is discussed in Section 8. Instruction Queue.

4.2.1 Original M68HC12 Queue Implementation

There are two 16-bit queue stages and one 16-bit buffer. Program

information is fetched in aligned 16-bit words. Unless buffering is required,

program information is first queued into stage 1, then advanced to stage 2

for execution.

At least two words of program information are available to the CPU when

execution begins. The first byte of object code is in either the even or odd

half of the word in stage 2, and at least two more bytes of object code are in

the queue.

The buffer is used when a program word arrives before the queue can

advance. This occurs during execution of single-byte and odd-aligned

instructions. For instance, the queue cannot advance after an aligned,

single-byte instruction is executed, because the first byte of the next

instruction is also in stage 2. In these cases, information is latched into the

buffer until the queue can advance.

4.2.2 HCS12 Queue Implementation

There are three 16-bit stages in the instruction queue. Instructions enter the

queue at stage 1 and shift out of stage 3 as the CPU executes instructions

and fetches new ones into stage 1. Each byte in the queue is selectable. An

opcode prediction algorithm determines the location of the next opcode in

the instruction queue.

4.3 Data Movement in the Queue

All queue operations are combinations of four basic queue movement

cycles. Descriptions of each of these cycles follows. Queue movement

cycles are only one factor in instruction execution time and should not be

confused with bus cycles.

HCS12 数据表(PDF) 48 Page - Freescale Semiconductor, Inc