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HCS12 数据表(PDF) 321 Page - Freescale Semiconductor, Inc |
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HCS12 数据表(HTML) 321 Page - Freescale Semiconductor, Inc |
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321 / 452 page ![]() S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 321 • Cycle 8.1/8.2 pushes the 8-bit CCR onto the stack, then updates the mask bits. – When an XIRQ interrupt causes an exception, both X and I are set, which inhibits further interrupts during exception processing. – When any other interrupt causes an exception, the I bit is set, but the X bit is not changed. • Cycle 9.1/9.2 is the third of three program word fetches that refill the instruction queue. It is the last cycle of exception processing. After this cycle the CPU starts executing the first cycle of the instruction at the head of the instruction queue. |
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