HCS12 datasheet(358/452 Pages) FREESCALE

358 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

358

Freescale Semiconductor

from processing consequents of one rule to starting to process antecedents

of the next rule. At this transition, the A accumulator is initialized to $FF to

prepare for the min operation to find the smallest fuzzy input. Also, if Rx is

$FE, the V bit is toggled to indicate the change from antecedents to

consequents, or consequents to antecedents.

During cycle 5.0, a new rule byte is read unless this is the last loop pass,

and Rx is $FF (marking the end of the rule list). This new rule byte will not

be used until cycle 4.0 of the next pass through the loop.

Between cycle 5.0 and 6.x, the V-bit is used to decide which of two paths to

take. If V is zero, antecedents are being processed and the CPU progresses

to cycle 6.0. If V is one, consequents are being processed and the CPU

goes to cycle 6.1.

During cycle 6.0, the current value in the A accumulator is compared to the

fuzzy input that was read in the previous cycle 4.0, and the lower value is

placed in the A accumulator (min operation). If Rx is $FE, this is the

transition between rule antecedents and rule consequents, and this min

operation is skipped (although the cycle is still used). No bus access takes

place during cycle 6.0 but cycle 6.x is considered an x type cycle because it

could be a byte write (cycle 6.1) or a free cycle (cycle 6.0 or 6.1 with Rx =

$FE or $FF).

If an interrupt arrives while the REV instruction is executing, REV can break

between cycles 4.0 and 5.0 in an orderly fashion so that the rule evaluation

operation can resume after the interrupt has been serviced. Cycles 5.2 and

6.2 are needed to adjust the PC and X index register so the REV operation

can recover after the interrupt. PC is adjusted backward in cycle 5.2 so it

points to the currently running REV instruction. After the interrupt, rule

evaluation will resume, but the values that were stored on the stack for index

registers, accumulator A, and CCR will cause the operation to pick up where

it left off. In cycle 6.2, the X index register is adjusted backward by one

because the last rule byte needs to be re-fetched when the REV instruction

resumes.

After cycle 6.2, the REV instruction is finished, and execution would

continue to the normal interrupt processing flow.

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