HCS12 datasheet(412/452 Pages) FREESCALE

412 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

412

Freescale Semiconductor

B.6.1 Constant Offset Indexing

The CPU12 offers three variations of constant offset indexing to optimize

the efficiency of object code generation.

The most common constant offset is 0. Offsets of 1, 2, 3, 4 are used fairly

often, but with less frequency than 0.

The 5-bit constant offset variation covers the most frequent indexing

requirements by including the offset in the postbyte. This reduces a load

accumulator indexed instruction to two bytes of object code, and matches

the object code size of the smallest M68HC11 indexed instructions, which

can only use X as the index register. The CPU12 can use X, Y, SP, or PC

as the index reference with no additional object code size cost.

The signed 9-bit constant offset indexing mode covers the same positive

range as the M68HC11 8-bit unsigned offset. The size was increased to

nine bits with the sign bit (ninth bit) included in the postbyte, and the

remaining 8 bits of the offset in a single extension byte.

The 16-bit constant offset indexing mode allows indexed access to the

entire normal 64-Kbyte address space. Since the address consists of 16

bits, the 16-bit offset can be regarded as a signed (–32,768 to +32,767) or

unsigned (0 to 65,535) value. In 16-bit constant offset mode, the offset is

supplied in two extension bytes after the opcode and postbyte.

HCS12 数据表(PDF) 412 Page - Freescale Semiconductor, Inc