HCS12 datasheet(424/452 Pages) FREESCALE

424 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

424

Freescale Semiconductor

B.8.11 Support for Memory Expansion

Bank switching is a common method of expanding memory beyond the

64-Kbyte limit of a CPU with a 64-Kbyte address space, but there are some

known difficulties associated with bank switching. One problem is that

interrupts cannot take place during the bank switching operation. This

increases worst case interrupt latency and requires extra programming

space and execution time.

Some HCS12 and M68HC12 variants include a built-in bank switching

scheme that eliminates many of the problems associated with external

switching logic. The CPU12 includes CALL and return-from-call (RTC)

instructions that manage the interface to the bank-switching system. These

instructions are analogous to the JSR and RTS instructions, except that the

bank page number is saved and restored automatically during execution.

Since the page change operation is part of an uninterruptable instruction,

many of the difficulties associated with bank switching are eliminated. On

HCS12 and M68HC12 derivatives with expanded memory capability, bank

numbers are specified by on-chip control registers. Since the addresses of

these control registers may not be the same in all derivatives, the CPU12

has a dedicated control line to the on-chip integration module that indicates

when a memory-expansion register is being read or written. This allows the

CPU to access the PPAGE register without knowing the register address.

The indexed indirect versions of the CALL instruction access the address of

the called routine and the destination page value indirectly. For other

addressing mode variations of the CALL instruction, the destination page

value is provided as immediate data in the instruction object code. CALL

and RTC execute correctly in the normal 64-Kbyte address space, thus

providing for portable code.

HCS12 数据表(PDF) 424 Page - Freescale Semiconductor, Inc