HCS12 datasheet(429/452 Pages) FREESCALE

429 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

429

much less efficient because extra steps are required to prepare inputs to the

EDIVS, and because EDIVS uses the Y index register. EDIVS uses a 32-bit

signed numerator and the C compiler would typically want to use a 16-bit

value (the size of an integer data type). The 16-bit C value would need to be

sign-extended into the upper 16 bits of the 32-bit EDIVS numerator before

the divide operation.

Operand size is also a potential problem in the extended multiply operations

but the difficulty can be minimized by putting the results in CPU registers.

Having higher precision math instructions is not necessarily a requirement

for supporting high-level language because these functions can be

performed as library functions. However, if an application requires these

functions, the code is much more efficient if the MCU can use native

instructions instead of relatively large, slow routines.

C.6 Conditional If Constructs

In the CPU12 instruction set, most arithmetic and data manipulation

instructions automatically update the condition code register, unlike other

architectures that only change condition codes during a few specific

compare instructions. The CPU12 includes branch instructions that perform

conditional branching based on the state of the indicators in the condition

codes register. Short branches use a single byte relative offset that allows

branching to a destination within about

±128 locations from the branch.

Long branches use a 16-bit relative offset that allows conditional branching

to any location in the 64-Kbyte map.

C.7 Case and Switch Statements

Case and switch statements (and computed GOTOs) can use PC-relative

indirect addressing to determine which path to take. Depending upon the

situation, cases can use either the constant offset variation or the

accumulator D offset variation of indirect indexed addressing.

C.8 Pointers

The CPU12 supports pointers by allowing direct arithmetic operations on

the 16-bit index registers (LEAS, LEAX, and LEAY instructions) and by

allowing indexed indirect addressing modes.

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