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HCS12 数据表(PDF) 142 Page - Freescale Semiconductor, Inc |
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HCS12 数据表(HTML) 142 Page - Freescale Semiconductor, Inc |
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142 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 142 Freescale Semiconductor Operation: If V = 0, then (PC) + $0002 + Rel ⇒ PC Simple branch Description: Tests the V status bit and branches if V = 0. BVC causes a branch when a previous operation on two’s complement binary values does not cause an overflow. That is, when BVC follows a two’s complement operation, a branch occurs when the result of the operation is valid. See 3.8 Relative Addressing Mode for details of branch execution. BVC Branch if Overflow Cleared BVC CCR Details: S X HIN Z V C –––––––– Source Form Address Mode Object Code Access Detail HCS12 M68HC12 BVC rel8 REL 28 rr PPP/P(1) PPP/P(1) 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken. Branch Complementary Branch Test Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r>m BGT 2E Z + (N ⊕ V) = 0 r ≤m BLE 2F Signed r ≥m BGE 2C N ⊕ V = 0 r<m BLT 2D Signed r=m BEQ 27 Z = 1 r ≠m BNE 26 Signed r ≤m BLE 2F Z + (N ⊕ V) = 1 r>m BGT 2E Signed r<m BLT 2D N ⊕ V = 1 r ≥m BGE 2C Signed r>m BHI 22 C + Z = 0 r ≤m BLS 23 Unsigned r ≥m BHS/BCC 24 C = 0 r<m BLO/BCS 25 Unsigned r=m BEQ 27 Z = 1 r ≠m BNE 26 Unsigned r ≤m BLS 23 C + Z = 1 r>m BHI 22 Unsigned r<m BLO/BCS 25 C = 1 r ≥m BHS/BCC 24 Unsigned Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple r=0 BEQ 27 Z = 1 r ≠0 BNE 26 Simple Always BRA 20 — Never BRN 21 Unconditional |
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