HCS12 datasheet(170/452 Pages) FREESCALE

170 / 452 page

Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

170

Freescale Semiconductor

Operation:

(Y : D)

÷ (X) ⇒ Y; Remainder ⇒ D

Description:

Divides a 32-bit unsigned dividend by a 16-bit divisor, producing a 16-bit

unsigned quotient and an unsigned 16-bit remainder. All operands and

results are located in CPU registers. If an attempt to divide by zero is made,

C is set and the states of the N, Z, and V bits in the CCR are undefined. In

case of an overflow or a divide by zero, the contents of the registers D and

Y do not change.

EDIV

Extended Divide 32-Bit by 16-Bit

(Unsigned)

EDIV

CCR Details:

HIN

––––

∆∆∆∆

N: Set if MSB of result is set; cleared otherwise

Undefined after overflow or division by zero

Z: Set if result is $0000; cleared otherwise

Undefined after overflow or division by zero

V: Set if the result was > $FFFF; cleared otherwise Undefined after

division by zero

C: Set if divisor was $0000; cleared otherwise

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

EDIV

INH

ffffffffffO

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