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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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MC68HC705P9CS 数据表(PDF) 33 Page - Freescale Semiconductor, Inc |
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MC68HC705P9CS 数据表(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 160 page  Memory Input/Output Register Summary MC68HC705P9 — Rev. 4.0 Technical Data MOTOROLA Memory 33 3.4 Input/Output Register Summary Addr. Name Bit 7 6543 21 Bit 0 $0000 Port A Data Register (PORTA) See page 83. Read: PA7PA6 PA5PA4PA3PA2PA1PA0 Write: Reset: Unaffected by reset $0001 Port B Data Register (PORTB) See page 85. Read: PB7 PB6 PB5 00 000 Write: Reset: Unaffected by reset $0002 Port C Data Register (PORTC) See page 89. Read: PC7PC6PC5PC4 PC3PC2PC1PC0 Write: Reset: Unaffected by reset $0003 Port D Data Register (PORTD) See page 92. Read: PD7 0 PD5 10 000 Write: Reset: Unaffected by reset $0004 Data Direction Register A (DDRA) See page 83. Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset: 00000 000 $0005 Data Direction Register B (DDRB) See page 86. Read: DDRB7 DDRB6 DDRB5 00 000 Write: Reset: 00000 000 $0006 Data Direction Register C (DDRC) See page 89. Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Write: Reset: 00000 000 $0007 Data Direction Register D (DDRD) See page 92. Read: 0 0 DDRD5 00 000 Write: Reset: 00000 000 = Unimplemented R = Reserved U = Unaffected Figure 3-2. I/O Register Summary (Sheet 1 of 4) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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