MC68HC705P9CS datasheet(84/160 Pages) FREESCALE

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Parallel Input/Output (I/O) Ports

Technical Data

MC68HC705P9 — Rev. 4.0

Parallel Input/Output (I/O) Ports

MOTOROLA

NOTE:

Avoid glitches on port A pins by writing to the port A data register before

changing data direction register A bits from 0 to 1.

Figure 7-4 shows the I/O logic of port A.

Figure 7-4. Port A I/O Circuit

Writing a logic one to a DDRA bit enables the output buffer for the

corresponding port A pin; a logic zero disables the output buffer.

When bit DDRAx is a logic one, reading address $0000 reads the PAx

data latch. When bit DDRAx is a logic zero, reading address $0000

reads the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 7-1 summarizes the

operation of the port A pins.

Table 7-1. Port A Pin Operation

Data Direction Bit

I/O Pin Mode

Accesses to Data Bit

Read

Write

Input, Hi-Z(1)

1. Hi-Z = high impedance

Latch(2)

2. Writing affects data register, but does not affect input.

Output

Latch

READ DATA DIRECTION REGISTER A ($0004)

WRITE DATA DIRECTION REGISTER A ($0004)

RESET

WRITE PORT A DATA REGISTER ($0000)

READ PORT A DATA REGISTER ($0000)

PAx

DDRAx

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