MC68HC705P9CS datasheet(72/160 Pages) FREESCALE

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Resets and Interrupts

Technical Data

MC68HC705P9 — Rev. 4.0

Resets and Interrupts

MOTOROLA

5.4.4 Interrupt Processing

The CPU takes the following actions to begin servicing an interrupt:

•

Stores the CPU registers on the stack in the order shown in

Figure 5-6

•

Sets the I bit in the condition code register to prevent further

interrupts

•

Loads the program counter with the contents of the appropriate

interrupt vector locations:

–

$1FFC and $1FFD (software interrupt vector)

–

$1FFA and $1FFB (external interrupt vector)

–

$1FF8 and $1FF9 (timer interrupt vector)

The return from interrupt (RTI) instruction causes the CPU to recover the

CPU registers from the stack as shown in Figure 5-6.

Figure 5-6. Interrupt Stacking Order

CONDITION CODE REGISTER

$00C0 (BOTTOM OF STACK)

$00C1

$00C2

•

ACCUMULATOR

INDEX REGISTER

PROGRAM COUNTER (HIGH BYTE)

PROGRAM COUNTER (LOW BYTE)

•

$00FD

$00FE

$00FF (TOP OF STACK)

UNSTACKING

ORDER

STACKING

ORDER

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