MC68HC705P9CS datasheet(42/160 Pages) FREESCALE

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Memory

Technical Data

MC68HC705P9 — Rev. 4.0

Memory

MOTOROLA

3.7 Mask Option Register

The mask option register (MOR) is an EPROM/OTPROM byte that is

programmable only with the bootloader function. The MOR controls:

•

LSB first or MSB first SIOP data transfer

•

Edge-triggered or edge- and level-triggered external interrupt pin

•

Enabled or disabled COP watchdog

To program the MOR, use the 5-step procedure given in 3.6.1.1 EPROM

Programming Register. Write to address $0900 in step 3.

SIOP — Serial I/O Port

The SIOP bit controls the shift direction into and out of the SIOP shift

1 = SIOP data transferred LSB first (bit 0 first)

0 = SIOP data transferred MSB first (bit 7 first)

IRQ — Interrupt Request

The IRQ bit makes the external interrupt function of the IRQ/VPP pin

level-triggered as well as edge-triggered.

1 = IRQ/VPP pin negative-edge triggered and low-level triggered

0 = IRQ/VPP pin negative-edge triggered only

COPE — COP Enable

COPE enables the COP watchdog. In applications that have wait

cycles longer than the COP watchdog timeout period, the COP

watchdog can be disabled by not programming the COPE bit to logic

one.

1 = COP watchdog enabled

0 = COP watchdog disabled

$0900

Bit 7

Bit 0

Read:

SIOP

IRQ

COPE

Write:

Reset:

Unaffected by reset

Erased:

= Unimplemented

Figure 3-5. Mask Option Register (MOR)

Freescale Semiconductor, Inc.

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