MC68HC705P9CS datasheet(90/160 Pages) FREESCALE

90 / 160 page

Parallel Input/Output (I/O) Ports

Technical Data

MC68HC705P9 — Rev. 4.0

Parallel Input/Output (I/O) Ports

MOTOROLA

Writing a logic one to a DDRC bit enables the output buffer for the

corresponding port C pin; a logic zero disables the output buffer.

When bit DDRCx is a logic one, reading address $0002 reads the PCx

data latch. When bit DDRCx is a logic zero, reading address $0002

reads the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 7-3 summarizes the

operation of the port C pins.

7.6 Port D

Port D is a 2-bit port with one I/O pin and one input-only pin. Port D

shares the input-only pin, PD7/TCAP, with the capture/compare timer.

PD7/TCAP is the timer input capture pin. The PD7/TCAP pin can always

be a general-purpose input, even if input capture interrupts are enabled.

Table 7-3. Port C Pin Operation

Data Direction Bit

I/O Pin Mode

Accesses to Data Bit

Read

Write

Input, Hi-Z(1)

1. Hi-Z = high impedance

Latch(2)

2. Writing affects data register, but does not affect input.

Output

Latch

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC705P9CS 数据表(PDF) 90 Page - Freescale Semiconductor, Inc