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MC68HC705P9CS 数据表(PDF) 82 Page - Freescale Semiconductor, Inc |
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MC68HC705P9CS 数据表(HTML) 82 Page - Freescale Semiconductor, Inc |
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82 / 160 page ![]() Parallel Input/Output (I/O) Ports Technical Data MC68HC705P9 — Rev. 4.0 82 Parallel Input/Output (I/O) Ports MOTOROLA Addr. Name: R/W Bit 7 6 5 4 3 2 1 Bit 0 $0000 Port A Data Register (PORTA) See page 83. Read: PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Write: Reset: Unaffected by reset $0001 Port B Data Register (PORTB) See page 85. Read: PB7 PB6 PB5 000 00 Write: Reset: Unaffected by reset $0002 Port C Data Register (PORTC) See page 88. Read: PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Write: Reset: Unaffected by reset $0003 Port D Data Register (PORTD) See page 91. Read: PD7 0 PD5 100 00 Write: Reset: Unaffected by reset $0004 Data Direction Register A (DDRA) See page 83. Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset: 000 000 00 $0005 Data Direction Register B (DDRB) See page 86. Read: DDRB7 DDRB6 DDRB5 000 00 Write: Reset: 000 000 00 $0006 Data Direction Register C (DDRC) See page 89. Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Write: Reset: 000 000 00 $0007 Data Direction Register D (DDRD) See page 92. Read: 0 0 DDRD5 000 00 Write: Reset: 000 000 00 = Unimplemented Figure 7-1. Parallel I/O Port Register Summary Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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