MC68HC705P9CS datasheet(80/160 Pages) FREESCALE

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Low Power Modes

Technical Data

MC68HC705P9 — Rev. 4.0

Low Power Modes

MOTOROLA

Figure 6-4 shows the effect of the STOP and WAIT instructions on the

CPU clock and the timer clock.

Figure 6-4. STOP/WAIT Clock Logic

6.4 Data-Retention Mode

In data-retention mode, the MCU retains RAM contents and CPU

DD voltages as low as 2.0 Vdc. The data-retention

feature allows the MCU to remain in a low-power consumption state

during which it retains data, but the CPU cannot execute instructions.

To put the MCU in data-retention mode:

1. Drive the RESET pin to logic zero.

2. Lower the V

DD voltage. The RESET pin must remain low

continuously during data-retention mode.

To take the MCU out of data-retention mode:

1. Return V

DD to normal operating voltage.

2. Return the RESET pin to logic one.

CPU CLOCK

INTERNAL CLOCK

÷ 2

TIMER CLOCK

ADC CLOCK

INTERNAL

OSCILLATOR

OSC1

OSC2

WAIT

STOP

Freescale Semiconductor, Inc.

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