MC68HC705P9CS datasheet(69/160 Pages) FREESCALE

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Resets and Interrupts

Interrupts

MC68HC705P9 — Rev. 4.0

Technical Data

MOTOROLA

Resets and Interrupts

5.4.1 Software Interrupt

The software interrupt (SWI) instruction causes a non-maskable

interrupt.

5.4.2 External Interrupt

An interrupt signal on the IRQ/VPP pin latches an external interrupt

request. When the CPU completes its current instruction, it tests the IRQ

latch. If the IRQ latch is set, the CPU then tests the I bit in the condition

code register. If the I bit is clear, the CPU then begins the interrupt

sequence.

The CPU clears the IRQ latch during interrupt processing, so that

another interrupt signal on the IRQ/VPP pin can latch another interrupt

request during the interrupt service routine. As soon as the I bit is cleared

during the return from interrupt, the CPU can recognize the new interrupt

request. Figure 5-4 shows the IRQ/VPP pin interrupt logic.

Figure 5-4. External Interrupt Logic

Setting the I bit in the condition code register disables external interrupts.

Interrupt triggering sensitivity of the IRQ/VPP pin is a programmable

option. The IRQ/VPP pin can be negative-edge triggered or negative-

edge- and low-level triggered. The level-sensitive triggering option

allows multiple external interrupt sources to be wire-ORed to the

CLR

LEVEL-SENSITIVE TRIGGER

(MOR OPTION)

VDD

EXTERNAL

INTERRUPT

REQUEST

RESET

VECTOR FETCH

IRQ/VPP

(FROM CCR)

Freescale Semiconductor, Inc.

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