MC68HC705P9CS datasheet(68/160 Pages) FREESCALE

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Resets and Interrupts

Technical Data

MC68HC705P9 — Rev. 4.0

Resets and Interrupts

MOTOROLA

5.2.3 COP Watchdog Reset

A timeout of the COP watchdog generates a COP reset. The COP

watchdog is part of a software error detection system and must be

cleared periodically to start a new timeout period. To clear the COP

watchdog and prevent a COP reset, write a logic zero to bit 0 (COPC) of

the COP register at location $1FF0.

5.3 Low-Voltage Protection

A drop in power supply voltage below the minimum operating VDD

voltage is called a brownout condition. A brownout while the MCU is in a

non-reset state can corrupt MCU operation and necessitate a power-on

reset to resume operation.

The best protection against brownout is an undervoltage sensing circuit

that pulls the RESET pin low when it detects a low-power supply voltage.

The undervoltage sensing circuit may be made of discrete components

or an integrated circuit can be used.

For information about brownout and the COP watchdog, see Section 8.

Computer Operating Properly Watchdog (COP).

5.4 Interrupts

The following sources can generate interrupts:

•

SWI instruction

•

IRQ/VPP pin

•

Capture/compare timer

An interrupt temporarily stops normal program execution to process a

particular event. An interrupt does not stop the operation of the

instruction being executed, but takes effect when the current instruction

completes its execution. Interrupt processing automatically saves the

CPU registers on the stack and loads the program counter with a user-

defined interrupt vector address.

Freescale Semiconductor, Inc.

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