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PPC8567CVTAQGGA 数据表(PDF) 22 Page - Freescale Semiconductor, Inc |
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PPC8567CVTAQGGA 数据表(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 139 page  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 22 Freescale Semiconductor DDR and DDR2 SDRAM Figure 3 provides the input timing diagram for the DDR SDRAM interface. tDISKEW can be calculated from tCISKEW. See Table 19 footnote 2. Figure 3. DDR SDRAM Input Timing Diagram 6.2.2 DDR SDRAM Output AC Timing Specifications Table 20. DDR SDRAM Output AC Timing Specifications At recommended operating conditions. Parameter Symbol 1 Min Max Unit Notes MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 3.75 10 ns 2 ADDR/CMD output setup with respect to MCK tDDKHAS ns 3 533 MHz 1.48 — 7 400 MHz 1.95 — 333 MHz 2.40 — ADDR/CMD output hold with respect to MCK tDDKHAX ns 3 533 MHz 1.48 — 7 400 MHz 1.95 — 333 MHz 2.40 — MCS[n] output setup with respect to MCK tDDKHCS ns 3 533 MHz 1.48 — 7 400 MHz 1.95 — 333 MHz 2.40 — MDQ[x] MDQS[n] MCK[n] MCK[n] tMCK tDISKEW tDISKEW D1 D0 |
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