PPC8567CVTAQGGA datasheet(97/139 Pages) FREESCALE

97 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

HDLC, BISYNC, Transparent and Synchronous UART

Figure 65 provides the AC test load.

Figure 65. AC Test Load

Outputs—Internal clock High Impedance

tHIKHOX

05.5

Outputs—External clock High Impedance

tHEKHOX

Inputs—Internal clock input setup time

tHIIVKH

6—

Inputs—External clock input setup time

tHEIVKH

4—

Inputs—Internal clock input Hold time

tHIIXKH

0—

Inputs—External clock input hold time

tHEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the

high state (H) until outputs (O) are invalid (X).

Table 77. Synchronous UART AC Timing Specifications

Characteristic

Symbol 2

Min

Max

Unit

Outputs—Internal clock delay

tHIKHOV

011

Outputs—External clock delay

tHEKHOV

114