PPC8567CVTAQGGA datasheet(78/139 Pages) FREESCALE

78 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Serial RapidIO

Figure 51. Compliance Test/Measurement Load

15 Serial RapidIO

This section describes the DC and AC electrical specifications for the RapidIO interface of the

MPC8568E, for the LP-Serial physical layer. The electrical specifications cover both single and

multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each

of three baud rates, 1.25, 2.50, and 3.125 GBaud.

Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to

driving two connectors across a backplane. A single receiver specification is given that will accept signals

from both the short run and long run transmitter specifications.

The short run transmitter should be used mainly for chip-to-chip connections on either the same printed

circuit board or across a single connector. This covers the case where connections are made to a mezzanine

(daughter) card. The minimum swings of the short run specification reduce the overall power used by the

transceivers.

The long run transmitter specifications use larger voltage swings that are capable of driving signals across

backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications

allow a distance of at least 50 cm at all baud rates.

All unit intervals are specified with a tolerance of +/– 100 ppm. The worst case frequency difference

between any transmit and receive clock will be 200 ppm.

To ensure interoperability between drivers and receivers of different vendors and technologies, AC

coupling at the receiver input must be used.

15.1

DC Requirements for Serial RapidIO SD_REF_CLK and

SD_REF_CLK

For more information, see Section 13.2, “SerDes Reference Clocks.”

PPC8567CVTAQGGA 数据表(PDF) 78 Page - Freescale Semiconductor, Inc