PPC8567CVTAQGGA datasheet(28/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet Interface and MII Management

8.2

FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this

section.

8.2.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI

specifications, since they have similar performance and are described in a source-synchronous fashion like

FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and

source clock in GMII fashion.

Input high current

(VIN = LVDD, VIN = TVDD)

IIH

—40

μA

1, 2, 3

Input low current

(VIN = GND)

IIL

–600

—

μA3

Notes:

1. LVDD supports eTSECs 1 and 2.

2. TVDD supports QE UCC1 and UCC2 ethernet ports.

3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 2 and Table 3.

Table 24. GMII, MII, RMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics

Parameters

Symbol

Min

Max

Unit

Notes

Supply voltage 2.5 V

LVDD/TVDD

2.37

2.63

1, 2

Output high voltage

(LVDD/TVDD = Min, IOH = –1.0 mA)

VOH

2.00

LVDD/TVDD + 0.3

—

Output low voltage

(LVDD/TVDD = Min, IOL = 1.0 mA)

VOL

GND – 0.3

0.40

—

Input high voltage

VIH

1.70

LVDD/TVDD + 0.3

—

Input low voltage

VIL

–0.3

0.70

—

Input high current

(VIN = LVDD, VIN = TVDD)

IIH

—10

μA1, 2, 3

Input low current

(VIN = GND)

IIL

–15

—

μA3

Note:

1. LVDD supports eTSECs 1 and 2.

2. TVDD supports QE UCC1 and UCC2 ethernet ports.

3. Note that the symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Table 2 and Table 3.

Table 23. GMII, MII, RMII, and TBI DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

Notes

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