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PPC8567CVTAQGGA 数据表(PDF) 14 Page - Freescale Semiconductor, Inc |
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PPC8567CVTAQGGA 数据表(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 139 page  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 14 Freescale Semiconductor Power Characteristics NOTE Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. In order to guarantee MCKE low during power-up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing for GVDD is not required. 3 Power Characteristics The power dissipation of VDD for various core complex bus (CCB) versus the core and QE frequency for MPC8568E is shown in Table 5. Note that this is based on the design estimate only. More accurate power number will be available after we have done the measurement on the silicon. Table 5. MPC8568E Power Dissipation CCB Frequency Core Frequency QE Frequency Typical 65 °C Typical 105°C Maximum Unit 400 800 400 8.7 12.0 13.0 W 400 1000 400 8.9 12.3 13.6 W 400 1200 400 11.3 15.7 16.9 W 533 1333 533 12.4 17.2 18.7 W Notes: 1. CCB Frequency is the SoC platform frequency which corresponds to DDR data rate. 2. Typical 65 °C based on VDD=1.1V, Tj=65. 3. Typical 105 °C based on VDD=1.1V, Tj=105. 4. Maximum based on VDD=1.1V, Tj=105. Table 6. Typical MPC8568E I/O Power Dissipation Interface Parameters GVDD BVDD OVDD LVDD TVDD XVDD Unit Comment 2.5 V 1.8 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V DDR/DDR2 333 MHz 0.76 0.50 W Data rate 64-bit with ECC 60% utilization 400 MHz 0.56 W 533 MHz 0.68 W Local Bus 33 MHz, 32b 0.07 0.04 W — 66 MHz, 32b 0.13 0.07 W — 133 MHz, 32b 0.24 0.14 W — PCI 33 MHz 0.04 W — 66 MHz 0.07 W — SRIO 4x, 3.125G 0.49 W — PCI Express 8x, 2.5G 0.71 W — |
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