PPC8567CVTAQGGA datasheet(18/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8568E. Table 10 provides the RESET initialization AC timing specifications for the DDR

SDRAM component(s).

Table 11 provides the PLL lock times.

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8568E. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

μs—

Minimum assertion time for SRESET

—

SYSCLKs

PLL input setup time with stable SYSCLK before HRESET negation

100

—

μs—

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

—

SYSCLKs

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR configs with

respect to negation of HRESET

—

SYSCLKs

Notes:

1. SYSCLK is the primary clock input for the MPC8568E.

Table 11. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

Platform PLL lock times

—

100

μs—

QE PLL lock times

—

100

μs—

CPU PLL lock times

—

100

μs—

PCI PLL lock times

—

100

μs—

Local bus PLL

—

100

μs—

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