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PPC8567CVTAQGGA 数据表(PDF) 87 Page - Freescale Semiconductor, Inc

部件名 PPC8567CVTAQGGA
功能描述  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications
PDF  139 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

PPC8567CVTAQGGA 数据表(HTML) 87 Page - Freescale Semiconductor, Inc

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
87
Serial RapidIO
Figure 55. Receiver Input Compliance Mask
15.9
Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause
47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by
Clause 47. In addition, the CJPAT test pattern defined in Annex 48A of IEEE 802.3ae-2002 is specified as
the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE 802.3ae-2002 is
recommended as a reference for additional information on jitter test methods.
15.9.1
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point
at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the
Table 64. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type
VDIFFmin (mV)
VDIFFmax (mV)
A (UI)
B (UI)
1.25 GBaud
100
800
0.275
0.400
2.5 GBaud
100
800
0.275
0.400
3.125 GBaud
100
800
0.275
0.400
1
0
VDIFF max
-VDIFF max
VDIFF min
-VDIFF min
Time (UI)
0
AB
1-B
1-A



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