PPC8567CVTAQGGA datasheet(47/139 Pages) FREESCALE

部件名	PPC8567CVTAQGGA

功能描述	MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications

PDF	139 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Local Bus

Figure 23. Local Bus AC Test Load

NOTE

PLL bypass mode is required when LBIU frequency is at or below 83 MHz.

When LBIU operates above 83 MHz, LBIU PLL is recommended to be

enabled.

Figure 24 to Figure 29 show the local bus signals.

Figure 24. Local Bus Signals (PLL Enabled)

Table 43 describes the timing parameters of the local bus interface at BVDD = 3.3 V with PLL disabled.

Table 43. Local Bus Timing Parameters—PLL Bypassed

Parameter

Symbol 1

Min

Max

Unit Notes

Local bus cycle time

tLBK

—

Local bus duty cycle

tLBKH/tLBK

—

Output

Z0 = 50 Ω

BVDD/2

RL = 50 Ω

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

tLBKHOV1

tLBKHOV2

tLBKHOV3

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

LALE

tLBIXKH1

tLBIVKH1

tLBIVKH2

tLBIXKH2

tLBKHOX1

tLBKHOZ1

tLBKHOX2

tLBKHOZ2

Input Signal:

LGTA

tLBOTOT

tLBKHOZ2

tLBKHOX2

tLBKHOV4

LUPWAIT

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