PPC8567CVTAQGGA datasheet(70/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

PCI Express

13.3

SerDes Transmitter and Receiver Reference Circuits

Figure 48 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 48. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below

(PCI Express, Serial Rapid IO or SGMII) in this document based on the application usage:

•

Section 14, “PCI Express”

•

Section 15, “Serial RapidIO”

Note that external AC Coupling capacitor is required for the above three serial transmission protocols with

the capacitor value defined in specification of each protocol section.

14 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8568E.

14.1

DC Requirements for PCI Express SD_REF_CLK and

SD_REF_CLK

For more information, see Section 13, “High-Speed Serial Interfaces (HSSI).”

14.2

AC Requirements for PCI Express SerDes Clocks

Table 50 lists AC requirements.

Table 50. SD_REF_CLK and SD_REF_CLK AC Requirements

Symbol

Parameter Description

Min

Typical

Max

Units

Notes

tREF

REFCLK cycle time

—

tREFCJ

REFCLK cycle-to-cycle jitter. Difference in the period of any two

adjacent REFCLK cycles

—

100

—

Receiver

Transmitter

SD_TXn

SD_RXn

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