PPC8567CVTAQGGA datasheet(30/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Ethernet Interface and MII Management

Timing diagrams for FIFO appear in Figure 7 and Figure 8.

Figure 7. FIFO Transmit AC Timing Diagram

Figure 8. FIFO Receive AC Timing Diagram

8.2.2

GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2.1

GMII Transmit AC Timing Specifications

Table 27 provides the GMII transmit AC timing specifications.

Table 27. GMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

GTX_CLK clock period

tGTX

—8.0

—

GTX_CLK duty cycle

tGTXH/tGTX

—

GMII data TXD[7:0], TX_ER, TX_EN setup time

tGTKHDV

2.5

—

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

tGTKHDX

0.5

—

5.0

GTX_CLK data clock rise time (20%-80%)

tGTXR

—1.0

2.0

GTX_CLK data clock fall time (80%-20%)

tGTXF

—1.0

2.0

EC_GTX_CLK125 clock rise time (20%-80%)

tG125R

—1.0

2.0

EC_GTX_CLK125 clock fall time (80%-20%)

tG125F

—1.0

2.0

tFIT

tFITH

tFITF

tFITDX

TXD[7:0]

TX_EN

GTX_CLK

TX_ER

tFITDV

tFITR

tFIR

tFIRH

tFIRF

tFIRR

RX_CLK

RXD[7:0]

RX_DV

RX_ER

valid data

tFIRDX

tFIRDV

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