PPC8567CVTAQGGA datasheet(12/139 Pages) FREESCALE

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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8568E.

Figure 2. Overshoot/Undershoot Voltage for BVDD/GVDD/LVDD/TVDD/OVDD

Three-speed Ethernet I/O voltage

LVDD

TVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

V—

PCI, DUART, system control and power management, I2C, and JTAG I/O

voltage

OVDD

3.3 V ± 165 mV

—

Local bus I/O voltage

BVDD

3.3 V ± 165 mV

2.5 V ± 125 mV

V—

Input voltage

DDR and DDR2 DRAM signals

MVIN

GND to GVDD

V—

DDR and DDR2 DRAM reference

MVREF

GND to GVDD/2

—

Three-speed Ethernet signals

LVIN

TVIN

GND to LVDD

GND to TVDD

V—

Local bus signals

BVIN

GND to BVDD

V—

PCI, DUART, SYSCLK, system control and power

management, I2C, and JTAG signals

OVIN

GND to OVDD

V—

Junction temperature range

0 to105

oC—

Table 3. Recommended Operating Conditions (continued)

Characteristic

Symbol

Recommended

Value

Unit Notes

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

B/G/L/T/OVDD + 20%

B/G/L/T/OVDD

B/G/L/T/OVDD + 5%

of tCLOCK

1. Note that tCLOCK refers to the clock period associated with the respective interface

VIH

VIL

Note:

For I2C and JTAG, tCLOCK references SYSCLK.

For DDR, tCLOCK references MCLK.

For eTSEC, tCLOCK references EC_GTX_CLK125.

For LBIU, tCLOCK references LCLK.

For PCI, tCLOCK references PCI_CLK or SYSCLK.

For SerDes, tCLOCK references SD_REF_CLK.

2. Note that with the PCI overshoot allowed (as specified above), the device

does not fully comply with the maximum AC ratings and device protection guideline

outlined in the PCI rev. 2.2 standard (section 4.2.2.3)

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