MPC8544E datasheet(26/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

Output differential voltage2,3,5

|VOD|

323

500

725

Equalization

setting: 1.0x

296

459

665

Equalization

setting: 1.09x

269

417

604

Equalization

setting: 1.2x

243

376

545

Equalization

setting: 1.33x

215

333

483

Equalization

setting: 1.5x

189

292

424

Equalization

setting: 1.71x

162

250

362

Equalization

setting: 2.0x

Output offset voltage

VOS

425

500

577.5

1, 4

Output impedance (single

ended)

—

Mismatch in a pair

ΔR

——

—

Change in VOD between 0 and 1

Δ|V

OD|—

—

Change in VOS between 0 and 1

ΔV

——

—

Output current on short to GND

ISA, ISB

——

—

Notes:

1. This will not align to DC-coupled SGMII.

2. |VOD| = |VSD2_TXn – VSD2_TXn|. |VOD| is also referred as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|.

3. The |VOD| value shown in the table assumes the following transmit equalization setting in the XMITEQCD (for SerDes 2 lane

2 and 3) bit field of MPC8544E SerDes 2 control register 1:

•The MSbit (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude—power up default);

•The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in this table.

4. VOS is also referred to as output common mode voltage.

5. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS2-Typ = 1.0 V, no common mode offset

variation (VOS = 500 mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and SD2_TX[n].

Table 24. DC Transmitter Electrical Characteristics (continued)

Parameter

Symbol

Min

Typ

Max

Unit

Notes

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