MPC8544E datasheet(92/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Package Description

6.The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k

Ω pull-up or pull-down

resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.”

7.The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-k

pull-up or pull-down resistors. See Section 19.3, “e500 Core PLL Ratio.”

8.Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or

because it has other manufacturing test functions. Therefore, this pin will be described as an I/O for boundary scan.

9.For proper state of these signals during reset, DMA_DACK[1] must be pulled down to GND through a resistor. DMA_DACK[0]

can be pulled up or left without a resistor. However, if there is any device on the net which might pull down the value of the

net at reset, then a pullup is needed on DMA_DACK[0].

10.This output is actively driven during reset rather than being three-stated during reset.

11.These JTAG pins have weak internal pull-up P-FETs that are always enabled.

12.These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking

and regulation.

13.Anode and cathode of internal thermal diode.

14.Treat pins AC7, T5, V2, and M7 as spare configuration pins cfg_spare[0:3]. The spare pins are unused POR config pins. It

is highly recommended that the customer provide the capability of setting these pins low (that is, pull-down resistor which

is not currently stuffed) in order to support new config options should they arise between revisions.

15.If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state

during reset.

16.This pin is only an output in FIFO mode when used as Rx flow control.

17.Do not connect.

18.These are test signals for factory use only and must be pulled up (100

Ω to 1 kΩ) to OV

DD for normal machine operation.

19.Independent supplies derived from board VDD.

20.Recommend a pull-up resistor (1 K~) be placed on this pin to OVDD.

21.The following pins must not be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE,

MSRCID[2:4], and ASLEEP.

22.This pin requires an external 4.7-k

Ω pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively

driven.

23.General-purpose POR configuration of user system.

24.When a PCI block is disabled, either the POR config pin that selects between internal and external arbiter must be pulled

down to select external arbiter if there is any other PCI device connected on the PCI bus, or leave the address pins as No

Connect or terminated through 2–10 k

Ω pull-up resistors with the default of internal arbiter if the address pins are not

connected to any other PCI device. The PCI block will drive the address pins if it is configured to be the PCI arbiter—through

POR config pins—irrespective of whether it is disabled via the DEVDISR register or not. It may cause contention if there is

any other PCI device connected on the bus.

25.MDIC0 is grounded through an 18.2-

Ω precision 1% resistor and MDIC1 is connected GV

DD through an 18.2-Ω precision

1% resistor. These pins are used for automatic calibration of the DDR IOs.

26.For SGMII mode.

27.Connect to GND.

28.For systems that boot from a local bus (GPCM)-controlled flash, a pull-up on LGPL4 is required.

Table 62. MPC8544E Pinout Listing (continued)

Signal

Package Pin Number

Pin Type

Power

Supply

Notes

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