MPC8544E datasheet(6/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

MPC8544E Overview

– Broadcast address (accept/reject)

– Hash table match on up to 512 multicast addresses

– Promiscuous mode

— Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet

programming models

— RMON statistics support

— 10-Kbyte internal transmit and 2-Kbyte receive FIFOs

— MII management interface for control and status

— Ability to force allocation of header information and buffer descriptors into L2 cache

•

OCeaN switch fabric

— Full crossbar packet switch

— Reorders packets from a source based on priorities

— Reorders packets to bypass blocked packets

— Implements starvation avoidance algorithms

— Supports packets with payloads of up to 256 bytes

•

Integrated DMA controller

— Four-channel controller

— All channels accessible by both the local and remote masters

— Extended DMA functions (advanced chaining and striding capability)

— Support for scatter and gather transfers

— Misaligned transfer capability

— Interrupt on completed segment, link, list, and error

— Supports transfers to or from any local memory or I/O port

— Selectable hardware-enforced coherency (snoop/no snoop)

— Ability to start and flow control each DMA channel from external 3-pin interface

— Ability to launch DMA from single write transaction

•PCI controller

— PCI 2.2 compatible

— One 32-bit PCI port with support for speeds from 16 to 66 MHz

— Host and agent mode support

— 64-bit dual address cycle (DAC) support

— Supports PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses

— Supports posting of processor-to-PCI and PCI-to-memory writes

— PCI 3.3-V compatible

— Selectable hardware-enforced coherency

MPC8544E 数据表(PDF) 6 Page - Freescale Semiconductor, Inc

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