MPC8544E datasheet(38/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

A summary of the single-clock TBI mode AC specifications for receive appears in Table 36.

A timing diagram for TBI receive appears in Figure 21.

Figure 21. TBI Single-Clock Mode Receive AC Timing Diagram

8.7.4

RGMII and RTBI AC Timing Specifications

Table 37 presents the RGMII and RTBI AC timing specifications.

Table 36. TBI Single-Clock Mode Receive AC Timing Specification

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

RX_CLK clock period

tTRR

7.5

8.0

8.5

—

RX_CLK duty cycle

tTRRH

—

RX_CLK peak-to-peak jitter

tTRRJ

——

250

—

Rise time RX_CLK (20%–80%)

tTRRR

——

1.0

—

Fall time RX_CLK (80%–20%)

tTRRF

——

1.0

—

RCG[9:0] setup time to RX_CLK rising edge

tTRRDV

2.0

—

RCG[9:0] hold time to RX_CLK rising edge

tTRRDX

1.0

—

Table 37. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with L/TVDD of 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

Data to clock output skew (at transmitter)

tSKRGT_TX

–500

500

Data to clock input skew (at receiver)

tSKRGT_RX

1.0

—

2.8

Clock period duration

tRGT

7.2

8.0

8.8

Duty cycle for 10BASE-T and 100BASE-TX

tRGTH/tRGT

3, 4

Rise time (20%–80%)

tRGTR

—

0.75

—

RX_CLK

RCG[9:0]

Valid Data

tTRRR

tTRRF

tTRRDV

tTRR

tTRRH

tTRRDX

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