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MPC8544E 数据表(PDF) 70 Page - Freescale Semiconductor, Inc |
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MPC8544E 数据表(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 117 page ![]() MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 70 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50- Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8544E SerDes reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. Figure 51. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 52 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8544E SerDes reference clock input’s DC requirement. Figure 52. Single-Ended Connection (Reference Only) 50 Ω 50 Ω SDn_REF_CLK SDn_REF_CLK Clock Driver 100 Ω differential PWB trace SerDes Refer. CLK Receiver Clock Driver CLK_Out CLK_Out LVPECL CLK Driver Chip R2 R2 R1 R1 10nF 10nF 10nF MPC8544E 50 Ω 50 Ω SDn_REF_CLK SDn_REF_CLK 100 Ω differential PWB trace SerDes Refer. CLK Receiver Clock Driver CLK_Out Single-Ended CLK Driver Chip 33 Ω Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. 50 Ω MPC8544E |
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