MPC8544E datasheet(79/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

PCI Express

17.5

Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 57 is specified using the passive compliance/test measurement load (see

Figure 58) in place of any real PCI Express RX component.

In general, the minimum receiver eye diagram measured with the compliance/test measurement load (see

Figure 58) will be larger than the minimum receiver eye diagram measured over a range of systems at the

input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is due

to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express

component to vary in impedance from the compliance/test measurement load. The input receiver eye

diagram is implementation specific and is not specified. RX component designer should provide additional

margin to adequately compensate for the degraded minimum receiver eye diagram (shown in Figure 57)

expected at the input receiver based on some adequate combination of system simulations and the return

loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using

the jitter median to locate the center of the eye diagram.

LTX-SKEW

Total skew

—

Skew across all lanes on a link. This includes

variation in the length of SKP ordered set (for

example, COM and one to five symbols) at

the RX as well as any delay differences

arising from the interconnect itself.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 58 should be used

as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 57). If the

clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must

be used as a reference for the eye diagram.

3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and

interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter

distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget

collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median

describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged

time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500

consecutive UI must be used as the reference for the eye diagram.

4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to

300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)

over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The

reference impedance for return loss measurements for is 50

Ω to ground for both the D+ and D– line (that is, as measured

by a vector network analyzer with 50-

Ω probes, see Figure 58). Note that the series capacitors CTX is optional for the return

loss measurement.

5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5-ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

6. The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps

ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be

measured at 300 mV above the RX ground.

7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm

using a minimization merit function. Least squares and median deviation fits have worked well with experimental and

simulated data.

Table 60. Differential Receiver (RX) Input Specifications (continued)

Symbol

Parameter

Min

Nom

Max

Units

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