MPC8544E datasheet(7/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

MPC8544E Overview

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Three PCI Express interfaces

— Two ×4 link width interfaces and one ×1 link width interface

— PCI Express 1.0a compatible

— Auto-detection of number of connected lanes

— Selectable operation as root complex or endpoint

— Both 32- and 64-bit addressing

— 256-byte maximum payload size

— Virtual channel 0 only

— Traffic class 0 only

— Full 64-bit decode with 32-bit wide windows

•

Power management

— Supports power saving modes: doze, nap, and sleep

— Employs dynamic power management, which automatically minimizes power consumption of

blocks when they are idle

•

System performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter-specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between

bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

•

System access port

— Uses JTAG interface and a TAP controller to access entire system memory map

— Supports 32-bit accesses to configuration registers

— Supports cache-line burst accesses to main memory

— Supports large block (4-Kbyte) uploads and downloads

— Supports continuous bit streaming of entire block for fast upload and download

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IEEE Std 1149.1™-compliant, JTAG boundary scan

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783 FC-PBGA package

MPC8544E 数据表(PDF) 7 Page - Freescale Semiconductor, Inc

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