MPC8544E datasheet(3/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

MPC8544E Overview

— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes

— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports

— Full ECC support

— Page mode support

– Up to 16 simultaneous open pages for DDR

– Up to 32 simultaneous open pages for DDR2

— Contiguous or discontiguous memory mapping

— Sleep mode support for self-refresh SDRAM

— On-die termination support when using DDR2

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast memory access via JTAG port

— 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)

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Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture.

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages

— Supports connection of an external interrupt controller such as the 8259 programmable

interrupt controller

— Four global high resolution timers/counters that can generate interrupts

— Supports a variety of other internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing.

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.

— Interrupt summary registers allow fast identification of interrupt source.

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Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,

IKE, WTLS/WAP, SSL/TLS, and 3GPP

— Four crypto-channels, each supporting multi-command descriptor chains

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Dynamic assignment of crypto-execution units via an integrated controller

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Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

— PKEU—public key execution unit

– RSA and Diffie-Hellman; programmable field size up to 2048 bits

– Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to

511 bits

— DEU—Data Encryption Standard execution unit

– DES, 3DES

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