MPC8544E datasheet(45/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Local Bus

10.2

Local Bus AC Electrical Specifications

Table 45 describes the general timing parameters of the local bus interface at BVDD = 3.3 V. For

information about the frequency range of local bus see Section 19.1, “Clock Ranges.”

High-level output voltage

(BVDD = min, IOH = –2 mA)

VOH

1.35

—

Low-level output voltage

(BVDD = min, IOL = 2 mA)

VOL

—0.45

—

Table 45. Local Bus General Timing Parameters (BVDD = 3.3 V)—PLL Enabled

Parameter

Symbol1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

7.5

Local bus duty cycle

tLBKH/tLBK

—

LCLK[n] skew to LCLK[m] or LSYNC_OUT

tLBKSKEW

—

150

7, 8

Input setup to local bus clock (except LUPWAIT)

tLBIVKH1

2.5

—

3, 4

LUPWAIT input setup to local bus clock

tLBIVKH2

1.85

—

3, 4

Input hold from local bus clock (except LUPWAIT)

tLBIXKH1

1.0

—

3, 4

LUPWAIT input hold from local bus clock

tLBIXKH2

1.0

—

3, 4

LALE output transition to LAD/LDP output transition

(LATCH setup and hold time)

tLBOTOT

1.5

—

Local bus clock to output valid (except LAD/LDP and LALE)

tLBKHOV1

—2.9

—

Local bus clock to data valid for LAD/LDP

tLBKHOV2

—2.8

—

Local bus clock to address valid for LAD

tLBKHOV3

—2.7

Local bus clock to LALE assertion

tLBKHOV4

—2.7

Output hold from local bus clock (except LAD/LDP and

LALE)

tLBKHOX1

0.7

—

Output hold from local bus clock for LAD/LDP

tLBKHOX2

0.7

—

Local bus clock to output high Impedance (except

LAD/LDP and LALE)

tLBKHOZ1

—2.5

Table 44. Local Bus DC Electrical Characteristics (1.8 V DC) (continued)

Parameter

Symbol

Min

Max

Unit

Notes

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