MPC8544E datasheet(71/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

16.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50

Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

Table 57 describes some AC parameters common to SGMII, and PCI Express protocols.

Figure 53. Differential Measurement Points for Rise and Fall Time

Table 57. SerDes Reference Clock Common AC Parameters

Parameter

Symbol

Min

Max

Unit

Notes

Rising Edge Rate

Rise Edge Rate

1.0

4.0

V/ns

2, 3

Falling Edge Rate

Fall Edge Rate

1.0

4.0

V/ns

2, 3

Differential Input High Voltage

VIH

+200

—

Differential Input Low Voltage

VIL

—

–200

Rising edge rate (SDn_REF_CLK) to falling edge rate

(SDn_REF_CLK) matching

Rise-Fall Matching

—

1, 4

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is

centered on the differential zero crossing. See Figure 53.

4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a

200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median

cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rise edge

rate of SDn_REF_CLK should be compared to the fall edge rate of SDn_REF_CLK, the maximum allowed difference should

not exceed 20% of the slowest edge rate. See Figure 54.

VIH = +200 mV

VIL = –200 mV

0.0 V

SDn_REF_CLK

minus

SDn_REF_CLK

Fall Edge Rate

Rise Edge Rage

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